Breadboard 8088 PC EEPROM, RAM & Address Decoder #7

Welcome to Breadboarding. This is video seven in the Breadboard PC series and in this video we adding an EEPROM, RAM and an address decoder . This is our high level plan in the previous video which I'll include a link to at the top of the screen here if you've missed out on it. We . We added a bus controller, latches and buffers and this allowed us to separate out the multiplexed data and address signals that the 8088 uses in order to fit everything into the 40 pin package . So if we take a look at the high level block diagram . So these are the previous steps that we've done adding the bus controller, buffers and latches and what we're going to be doing in this video is adding an address decoder which is going to look at some of the higher address lines and is then going to provide chip enable signals for the read only memory and also for the RAM. So we do . So we do need to decide the memory map for the address decoder . So the 512K of RAM is going to be in the lower block so this is going to be the 0 to 8 . Then the PIA for the moment I'm not going to use the IO ports I'm going to just use the memory mapped ports just like the 6800 series used at some point in time . I'll switch over to use IO ports and then the ROM needs to be in the top 32K of the address space so that will be F8000 up to the top of the memory range . That's what we're going to have to configure our address decoder so that we get the ROM and RAM and PIA in the right places . The original PC-XT schematics aren't that useful because they used dynamic random access memory which was a lot more complicated than the static RAM we're going to be using and also used older style memory chips for the ROM . So what we're going to be doing is using the design from the XI 8088